View CY7C4804V25_212389.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

5/0251
ADVANCE INFORMATION
CY7C4808V25 CY7C4806V25 CY7C4804V25
2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO w/Bus Matching
Features
* High-speed, low-power, unidirectional, first-in first-out (FIFO) memories w/bus matching capabilities * 64K x 80 (CY7C4808V25) * 16K x 80 (CY7C4806V25) * 4K x 80 (CY7C4804V25) * 2.5V 125 mV power supply * Fabricated using Cypress 0.21-micron CMOS Technology for optimum speed/power * Individual clock frequency up to 200 MHz (5 ns read/write cycle times) * High-speed access with tA = 3.5 * Bus matching on both ports: x80, x40, x20, x10 * Free-running CLKA and CLKB. Clocks may be asynchronous or coincident * CY standard or First-Word Fall-Through modes * Serial and parallel programming of Almost Empty/Full flags, each with 3 default values (8, 16, 64) * Master and Partial reset capability * Retransmit capability * All I/Os are 1.5V HSTL * Big or Little Endian format on Port B * 288 FBGA 19 mm x 19 mm (1.0-mm ball pitch) packaging * Width and depth expansion capability
Preliminary Top Level Block Diagram
CLKA CSA ENA MBA SIZE1A SIZE2A MBF IM CLKB
Port A Control Logic
MailBox Register
Port B Control Logic
CSB ENB MBB BE/FWFT SIZE1B SIZE2B RT/SPM OE
A79-0
80
Write Pointer
Read Pointer
Bus Matching Output Register
Bus Matching Input Register
Write Data Path Logic
Read Data Path Logic
4K/16K/64K x80 Dual Ported Memory
80
B79-0
4K/16K/64K x80 Dual Ported Memory
MRS PRS
FIFO Reset Logic Status Flag Logic
FF/IR AF
EF/OR AE TDO
FS0/SD FS1/SEN
Programmable Flag Offset Registers
JTAG/BIST Controller
TDI
TCK
TMS
TRST
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 December 16, 1999
ADVANCE INFORMATION
Functional Description
The CY7C480XV25 family of FIFOs is high-speed, low-power, CMOS Synchronous (clocked) FIFO memories, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of the clock on either port by the enable signal. The clocks for each port are independent of one another and can be asynchronous or coincident. The enable for each port is arranged to provide a simple unidirectional interface between microprocessors and/or buses with synchronous control. Two kinds of reset are available on the CY7C480XV25: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big Endian or Little Endian byte arrangement, selects the CY standard or First-Word Fall-Through (FWFT) mode, and determines the configuration of the programmable flags. The flags can be programmed either in serial mode or in parallel mode. The FIFO also comes with three possible default flag offset settings: 8, 16, or 64. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. The CY7C480XV25 have two modes of operation: CY Standard Mode or First-Word Fall-Through Mode (FWFT). In the CY Standard Mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the FWFT Mode, the first long-word (80-bit-wide) written to an empty FIFO appears automatically on the outputs, and no read operation is required. Nevertheless, access-
CY7C4808V25 CY7C4806V25 CY7C4804V25
ing subsequent words does necessitate a formal read request. FWFT mode is primarily used for cascading 2 or more FIFOs. The FIFO has an EF_OR flag on port B and FF_IR flag on Port A. The EF and FF functions are selected in the CY Standard Mode. EF indicates whether or not the FIFO memory is empty. FF shows whether or not the memory is full. The IR and OR functions are selected in the First-Word Fall-Through mode. IR indicates whether or not the FIFO has memory locations available. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. The FIFO has a programmable Almost Empty flag (AE) and a programmable Almost Full flag (AF). AE indicates the number of words left in the FIFO memory is at the user-defined amount. AF indicates the number of words written into the FIFO memory has achieved a predetermined amount. FF_IR and AF flags are synchronized to port A clock that writes data into its array. EF_OR and AE flags are synchronized to Port B clock that reads data from its array. Programmable offsets for AE and AF are loaded in parallel via Port A or in serial via the SD input. The Serial Programming Mode pin (SPM) makes this selection. Three default offsets setting are also provided. The AE threshold can be set at 8, 16 or 64 locations from the empty boundary and AF threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the Power-Down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power-Down state. The CY7C480XV25 FIFOs are characterized for operation from 0C to 70C commercial, and from -40C to 85C industrial.
Selection Guide
CY7C480XV25-200 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) 200 3.5 5 0.6 0.6 3.5 CY7C480XV25-166 166 4 6 0.6 0.6 4
CY7C4808V25 Density Package 64K x 80 288 FBGA
CY7C4806V25 16K x 80 288 FBGA
CY7C4804V25 4K x 80 288 FBGA
2
ADVANCE INFORMATION
Pin Description
Pin VCC_IO GND_io VCC_INT GND_int Vref MR PR A0-A79 B0-B79 ENA ENB MBA MBB CSA CSB OE CLKA CLKB BE_FWFT SIZE1A, SIZE2A SIZE1B, SIZE2B RT_SPM TDI, TDO, TCK, TMS, TRST FS1_SEN, FS0_SD EF_OR FF_IR AE AF Description Power supply for I/Os Ground pins for I/Os Power supply for internal logic Ground pins for internal logic Reference voltage Master reset Partial reset Input data bus Output data bus Port A enable pin Port B enable pin Port A Mailbox select Port B Mailbox select Port A chip select Port B chip select Output enable Port A clock Port B clock
CY7C4808V25 CY7C4806V25 CY7C4804V25
Big/Little Endian and CY Standard/First-Word Fall-Through mode select pin Port A bus size configuration pins Port B bus size configuration pins Retransmit pin/serial programming select JTAG pins Programmable flags configuration pins Empty/output ready flag (Port B) Full/input ready flag (Port A) Programmable almost empty flag (Port B) Programmable almost full flag (Port A)
3
ADVANCE INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied ...............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .........................................-0.5V to VCC+0.5V DC Input Voltage ......................................-0.5V to VCC+0.5V Output Current into Outputs (LOW) .............................20 mA
CY7C4808V25 CY7C4806V25 CY7C4804V25
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.5V 125 mV 2.5V 125 mV
DC Specifications (All I/Os will be at HSTL level)
CY7C480XV25 Parameter VCC _INT VCC_IO VREF VOH VOL VIH VIL IIX IOZL,IOZH ICC ISB Description Power Supply Voltage I/O Supply Voltage Input Reference Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current VCC _INT = Max. IOUT = 0 mA Typical value = 0.75V IOH > 16 mA IOL > 1-16 mA Test Conditions Min. 2.4 1.4 0.7 1 VSS 0.7 - 0.3 -10 -10 Max. 2.6 1.9 1.0 1.9 0.7 1.6 0.9 +10 +10 100 10 Unit V V V V V V V A A mA mA
AC Specifications (A 50 load terminated into 0.75V is used with VCC of 2.5V 125 mV)
CY7C4D80XV25 Parameter FMAX tCYC tSD tHD tA Description Max. Frequency Clock Cycle Time Input Data Set-Up Time Input Data Hold Time Access Time 5 0.6 0.6 3.5 Min. Max. 200 Unit MHz ns ns ns ns
4
ADVANCE INFORMATION
Timing Parameters
7C480XV25-200 Parameter fS tCLK tCLKH tCLKL tDS tENS tRSTS tFSS tBES tSMPS tSDS tSENS tFWS tDH tENH tRSTH tFSH tBEH tSPMH tSDH tSENH tSPH tSKEW1 tSKEW2 tA tWFF tREF tPAE tPAF tPMF tPMR tMDV tRSF tEN tDIS tPRT tRTR Document #: 38-00874-A 25 45 5 2.5 2.5 0.6 1.5 2 2 2 2 1.5 1.5 0 0.6 0 0 0 0 0 0 0 0 2.5 2.5 3.5 3 3 3 3 3 3.5 3.5 4 1.5 1.5 25 45 Min. Max. 200 6 3 3 0.6 2 2 5 5 5 2 2 0 0.6 0 0 0 0 0 0 0 0 5 5 4 4 4 4 4 4 4 4 4 4 4 7C480XV25-166 Min.
CY7C4808V25 CY7C4806V25 CY7C4804V25
Max. 166
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY7C4804V25

	To Download CY7C4804V25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .